1. Field of the Invention
The present invention relates to electronic design automation for an integrated circuit and, more particularly, to avoiding conflicts between constraints associated with objects that define the circuit.
2. Description of Related Art
Integrated circuit (IC) designers often use electronic design automation (EDA) software to assist in the design process. IC design using EDA software generally involves an iterative process whereby a circuit layout of the IC is usually perfected. State-of-the-art EDA software utilizes one or more optimization algorithms and design intent data to transform circuit schematic into a circuit layout that will perform a desired operation. Each such algorithm is a constraint-driven optimization algorithm and the design intent data is captured in constraints associated with objects that define the circuit, i.e., circuit objects, that the algorithm utilizes for placement of the circuit objects.
Throughout the design process, the designer may use one or more optimization algorithms, each possibly having a different set of constraints. When design iterations are performed, constraints from later stages of the design process are often used as input data for a new optimization algorithm. With ever-increasing design complexity, the number and diversity of constraints and the management operations needed to prepare the constraints for use with optimization algorithm(s) increases.
A top-down design methodology is commonly employed with EDA software to manage the complexity of the design. In this methodology, the designer designs an IC by hierarchically defining high level circuit structures of the circuit together with associated design goals and constraints, and then decomposes each circuit structure into smaller and smaller components. At higher levels in the IC design, the designer specifies constraints on the behavior of each circuit structure that needs to be transformed into circuit object constraints and electrical parameter constraints using simulation algorithms, circuit sizing algorithms and other such algorithms. Also, at higher levels in the IC design, organizational constraints on the generic placement of the circuit objects may be created which will be used by a placement algorithm to determine the possible location of a given circuit object in the circuit layout. At lower levels in the IC design, the size of each circuit object and the electrical constraints of the circuit are used to derive geometrical constraints that will be used by one or more placement algorithms to derive the precise position of the circuit objects in the circuit layout. Circuit objects can include devices, pins, rails and conductor networks that define the wiring that connects the devices, the pins and the rails.
After top-down realization of the IC design, the result is used to verify whether the higher-lever constraints have been met in a bottom-up fashion. Design iterations are often needed to perfect the IC design wherefrom constraints can be extracted to be used by higher level operations. Throughout the entire design process, designers provide each algorithm with a valid constraint set while also transforming constraint sets between the output of a given algorithm and the input of the next algorithm(s).
Two aspects of managing constraints in a top-down design methodology include: (1) maintaining a viable set of constraints for each algorithm that exists in the design flow utilized by the methodology; and (2) providing a work-flow mechanism to organize and transform constraints between the algorithms used such that the design process can be easily controlled and tuned by the designer.
While several automated solutions have been proposed to manage constraints, these solutions have limitations that restrict their utility. Specifically, prior solutions are limited by the lack of generality and completeness. Various solutions for verification of a constraint set for a given optimization algorithm have been proposed, but they lack the extensibility needed to allow for new algorithms or new constraints to be added, or lack the ability to perform cross-checking between different sets of constraints. Prior solutions for managing constraints through a work-flow are targeted to specific applications and cannot be extended to manage generic work-flow requirements. Also, none of the previous solutions allows user customization and intervention in the constraint management process.
It would therefore be advantageous to provide an improved constraint management method that avoids the above limitations and others by providing a scalable solution for forming viable constraint sets for the algorithms employed in a given design flow and that allows users to manage and transform constraints throughout the workflow. It would also be advantageous to provide a method for avoiding conflicts between constraints associated with objects that define a circuit. Still other advantages will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.